1. product profile 1.1 general description 160 w ldmos power transistor for base st ation applications at frequencies from 1800 mhz to 2050 mhz, also suitable for operation at 1495 mhz to 1511 mhz. [1] test signal: 3gpp; test model 1; 64 dpch; par = 8.4 db at 0.01 % probability on ccdf; carrier spacing 5 mhz. [2] test signal: 3gpp; test model 1; 64 dpch; par = 7.2 db at 0.01 % probability on ccdf. 1.2 features and benefits ? excellent ruggedness ? high efficiency ? low thermal resistance provid ing excellent thermal stability ? designed for broadband operation (1800 mhz to 2050 mhz) ? lower output capacitance for improved performance in doherty applications ? designed for low memory effects prov iding excellent pre-distortability ? internally matched for ease of use ? integrated esd protection ? compliant to directive 2002/ 95/ec, regarding restriction of hazardous substances (rohs) 1.3 applications ? rf power amplifiers fo r base stations and multi carrier applications in the 1800 mhz to 2050 mhz frequency range blf7g21l-160p; blf7g21ls-160p power ldmos transistor rev. 3 ? 10 february 2014 product data sheet table 1. typical performance typical rf performance at t case = 25 ? c in a common source class-ab production test circuit. mode of operation f i dq v ds p l(av) g p ? d acpr (mhz) (ma) (v) (w) (db) (%) (dbc) 2-carrier w-cdma 1930 to 1990 1080 28 45 18 34 ? 30 [1] 1-carrier w-cdma 1930 to 1990 1080 28 50 18.0 36 ? 34 [2]
blf7g21l-160p_7g21ls-160p all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 3 ? 10 february 2014 2 of 15 nxp semiconductors blf7g21l-160p; blf7g21ls-160p power ldmos transistor 2. pinning information [1] connected to flange. 3. ordering information 4. limiting values table 2. pinning pin description simplified outline graphic symbol blf7g21l-160p (sot1121a) 1drain1 2drain2 3gate1 4gate2 5source [1] blf7g21ls-160p (sot1121b) 1drain1 2drain2 3gate1 4gate2 5source [1] v \ p v \ p table 3. ordering information type number package name description version blf7g21l-160p - flanged ldmost ceramic package; 2 mounting holes; 4 leads sot1121a blf7g21ls-160p - earless flanged ceramic package; 4 leads sot1121b table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ds drain-source voltage - 65 v v gs gate-source voltage ? 0.5 +13 v i d drain current - 32.5 a t stg storage temperature ? 65 +150 ?c t j junction temperature - 200 ?c
blf7g21l-160p_7g21ls-160p all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 3 ? 10 february 2014 3 of 15 nxp semiconductors blf7g21l-160p; blf7g21ls-160p power ldmos transistor 5. thermal characteristics 6. characteristics 7. test information table 5. thermal characteristics symbol parameter conditions typ unit r th(j-c) thermal resistance from junction to case t case =80 ?c; p l = 100 w 0.41 k/w table 6. characteristics t j = 25 ? c; per section unless otherwise specified. symbol parameter conditions min typ max unit v (br)dss drain-source breakdown voltage v gs =0v; i d =0.9ma 65 - - v v gs(th) gate-source threshold voltage v ds = 10 v; i d = 90 ma 1.5 1.9 2.3 v i dss drain leakage current v gs =0v; v ds =28v - - 2 ? a i dsx drain cut-off current v gs =v gs(th) + 3.75 v; v ds =10v 14 - - a i gss gate leakage current v gs =11v; v ds = 0 v - - 200 na g fs forward transconductance v ds =10v; i d =4.5a - 7 - s r ds(on) drain-source on-state resistance v gs =v gs(th) + 3.75 v; i d =3.15a -0.15- ? table 7. application information mode of operation: 2-carrier w-cdma; par 8. 4 db at 0.01 % probability on ccdf; 3gpp test model 1; 64 pdpch; f 1 = 1932.5 mhz; f 2 = 1937.5 mhz; f 3 = 1982.5 mhz; f 4 = 1987.5 mhz; rf performance at v ds = 28 v; i dq = 1080 ma; t case = 25 ? c; unless otherwise specified; in a class-ab production test circuit. symbol parameter conditions min typ max unit g p power gain p l(av) = 45 w 17.0 18.0 - db rl in input return loss p l(av) = 45 w - ? 15 ? 8db ? d drain efficiency p l(av) = 45 w 31 34 - % acpr 5m adjacent channel power ratio (5 mhz) p l(av) = 45 w ? 30 ? 25 dbc acpr 10m adjacent channel power ratio (10 mhz) p l(av) = 45 w - - - dbc table 8. application information mode of operation: 1-carrier w-cdma; par 7. 2 db at 0.01 % probability on ccdf; 3gpp test model 1; 64 pdpch; f 1 = 1932.5 mhz; f 2 = 1987.5 mhz; rf performance at v ds = 28 v; i dq = 1080 ma; t case = 25 ? c; unless otherwise specified; in a class-ab production test circuit. symbol parameter conditions min typ max unit par o output peak-to-average ratio p l(av) =80w; at 0.01 % probability on ccdf 4.0 4.5 - db
blf7g21l-160p_7g21ls-160p all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 3 ? 10 february 2014 4 of 15 nxp semiconductors blf7g21l-160p; blf7g21ls-160p power ldmos transistor 7.1 ruggedness in class-ab operation the blf7g21l-160p and blf7g21ls-160p are capable of withstanding a load mismatch corresponding to vswr = 10 : 1 through all phases under the following conditions: v ds =28v; i dq =1080ma; p l = 160 w (cw), f = 1805 mhz, v ds =28v; i dq =350ma; p l = 31.6 w (is-95); p l = 90 w (pulsed cw, ? =10%, t p =100 ? s, per section), f = 1495 mhz. 7.2 cw v ds = 28 v; i dq = 1080 ma. (1) f = 1930 mhz (2) f = 1960 mhz (3) f = 1990 mhz fig 1. power gain and drain efficiency as function of load power; typical values 3 / g % p d d q * s g % '
blf7g21l-160p_7g21ls-160p all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2014. all rights reserved. product data sheet rev. 3 ? 10 february 2014 5 of 15 nxp semiconductors blf7g21l-160p; blf7g21ls-160p power ldmos transistor 7.3 1-carrier w-cdma v ds = 28 v; i dq = 1080 ma. (1) f = 1930 mhz (2) f = 1960 mhz (3) f = 1990 mhz v ds = 28 v; i dq = 1080 ma. (1) f = 1930 mhz (2) f = 1960 mhz (3) f = 1990 mhz fig 2. power gain and drain efficiency as function of load power; typical values fig 3. adjacent channel power ratio (5 mhz) and adjacent channel power ratio (10 mhz) as a function of load power; typical values 3 / g % p d d q * s g % ' 3 / g % p d d q $ & |